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ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 ISO7842 ISO7842f high-performance, 8000 v pk reinforced quad-channel digital isolator 1 features 3 description the ISO7842 is a high-performance, quad-channel 1 ? signaling rate: up to 100 mbps digital isolator with 8000 v pk isolation voltage. this ? wide supply range: 2.25 v to 5.5 v device has reinforced isolation certifications ? 2.25 v to 5.5 v level translation according to vde, csa, and cqc. the isolator provides high electromagnetic immunity and low ? wide temperature range: ? 55 c to 125 c emissions at low power consumption, while isolating ? low power consumption, typical 1.7 ma per cmos or lvcmos digital i/os. each isolation channel at 1 mbps channel has a logic input and output buffer separated ? low propagation delay: 11 ns typical by silicon dioxide (sio 2 ) insulation barrier. this device (5 v supplies) comes with enable pins which can be used to put the respective outputs in high impedance for multi-master ? industry leading cmt(min): 100 kv/ s driving applications and to reduce power ? robust electromagnetic compatibility (emc) consumption. iso784 2 has two forward and two ? system-level esd, eft, and surge immunity reverse-direction channels. if the input power or signal is lost, default output is ' high ' for the iso784 2 ? low emissions device and ' low ' for the iso784 2f device. see device ? isolation barrier life: > 25 years functional modes for further details. used in ? wide body soic-16 package and extra-wide conjunction with isolated power supplies, this device body soic-16 package options prevents noise currents on a data bus or other circuits from entering the local ground and interfering ? safety and regulatory approvals: with or damaging sensitive circuitry. through ? 8000 v pk reinforced isolation per din v vde innovative chip design and layout techniques, v 0884-10 (vde v 0884-10):2006-12 electromagnetic compatibility of iso784 2 has been ? 5.7 kv rms isolation for 1 minute per ul 1577 significantly enhanced to ease system-level esd, eft, surge and emissions compliance. iso784 2 is ? csa component acceptance notice 5a, iec available in 16-pin soic wide-body (dw) package 60950-1, iec 60601-1 and iec 61010-1 end and extra-wide body (dww) packages. equipment standards ? cqc certification per gb4943.1-2011 device information (1) ? dw package certifications complete; dww part number package body size (nom) certifications planned soic, dw (16) 10.30 mm 7.50 mm iso784 2 / extra wide soic, iso784 2f 10.30 mm 14.0 mm 2 applications dww (16) ? industrial automation (1) for all available packages, see the orderable addendum at the end of the data sheet. ? motor control ? power supplies spacer ? solar inverters ? medical equipment ? hybrid electric vehicles simplified schematic (1) v cci and gndi are supply and ground connections respectively for the input channels. (2) v cco and gndo are supply and ground connections respectively for the output channels. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. outx gndo gndi inx v cco v cci isolation capacitor enx productfolder sample &buy technical documents tools & software support &community
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com table of contents 8.1 overview ................................................................. 15 1 features .................................................................. 1 8.2 functional block diagram ....................................... 15 2 applications ........................................................... 1 8.3 feature description ................................................. 16 3 description ............................................................. 1 8.4 device functional modes ........................................ 20 4 revision history ..................................................... 2 9 application and implementation ........................ 22 5 pin configuration and functions ......................... 4 9.1 application information ............................................ 22 6 specifications ......................................................... 5 9.2 typical application .................................................. 22 6.1 absolute maximum ratings ...................................... 5 10 power supply recommendations ..................... 24 6.2 esd ratings .............................................................. 5 11 layout ................................................................... 25 6.3 recommended operating conditions ....................... 5 11.1 layout guidelines ................................................. 25 6.4 thermal information .................................................. 6 11.2 layout example .................................................... 25 6.5 power dissipation characteristics ............................ 6 12 device and documentation support ................. 26 6.6 electrical characteristics, 5 v ................................... 7 12.1 documentation support ........................................ 26 6.7 electrical characteristics, 3.3 v ................................ 8 12.2 related links ........................................................ 26 6.8 electrical characteristics, 2.5 v ................................ 9 12.3 community resources .......................................... 26 6.9 switching characteristics, 5 v ................................ 10 12.4 trademarks ........................................................... 26 6.10 switching characteristics, 3.3 v ........................... 10 12.5 electrostatic discharge caution ............................ 26 6.11 switching characteristics, 2.5 v ........................... 11 12.6 glossary ................................................................ 26 6.12 typical characteristics .......................................... 12 13 mechanical, packaging, and orderable 7 parameter measurement information ................ 13 information ........................................................... 26 8 detailed description ............................................ 15 4 revision history changes from revision c (july 2015) to revision d page ? added features : dw package certifications complete; dww certifications planned ......................................................... 1 ? added text to the description : and extra-wide body (dww) packages. ............................................................................... 1 ? added package: extra wide soic, dww (16) to the device informatio n table ..................................................................... 1 ? changed the min value of cmti in electrical characteristics, 5 v , 5 v table from: 70 to: 100 kv/ s, deleted the typ value of 100 kv/ s .......................................................................................................................................................... 7 ? added the supply current - ISO7842dw and ISO7842fdw section to the electrical characteristics, 5 v ......................... 7 ? added the supply current - ISO7842dww and ISO7842fdww section to the electrical characteristics, 5 v ................... 7 ? changed the min value of cmti in electrical characteristics, 3.3 v , 5 v table from: 70 to: 100 kv/ s, deleted the typ value of 100 kv/ s .......................................................................................................................................................... 8 ? added the supply current - ISO7842dw and ISO7842fdw section to the electrical characteristics, 3.3 v ...................... 8 ? added the supply current - ISO7842dww and ISO7842fdww section to the electrical characteristics, 3.3 v ................ 8 ? changed the min value of cmti in electrical characteristics, 2.5 v , 5 v table from: 70 to: 100 kv/ s, deleted the typ value of 100 kv/ s .......................................................................................................................................................... 9 ? added the supply current - ISO7842dw and ISO7842fdw section to the electrical characteristics, 2.5 v ...................... 9 ? added the supply current - ISO7842dww and ISO7842fdww section to the electrical characteristics, 2.5 v ................ 9 ? added the 16-dww package to table 1 ............................................................................................................................. 16 ? added the dww package information to table 2 ................................................................................................................ 17 ? added the dww package inforamtion to table 4 ................................................................................................................ 18 ? added text to the application information section: " isolation voltage per ul 1577. " ......................................................... 22 2 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 changes from revision b (april 2015) to revision c page ? added device iso7482f to the datasheet ............................................................................................................................. 1 ? changed the description to include: " default output is ' high ' for the ISO7842 device and ' low ' for the ISO7842f device. .. 1 ? changed from: t plh and t phl at 5.5v to: t plh and t phl at 5.0 v ........................................................................................... 12 ? changed figure 9 ................................................................................................................................................................. 14 ? changed figure 13 , added figure 14 ................................................................................................................................. 19 ? added the device i/o schematics section .......................................................................................................................... 21 changes from revision a (november 2014) to revision b page ? changed the document title from: " quad-channel digital isolator " to: " quad-channel 2/2 digital isolator " ....................... 1 ? added features 2.25 v to 5.5 v level translation ................................................................................................................ 1 ? changed features from: wide body soic-16 package to: wide body and extra-wide body soic-16 package options .................................................................................................................................................................................. 1 ? changed the safety and regulatory approvals list of features ............................................................................................ 1 ? changed the simplified schematic and added notes 1 and 2 ............................................................................................... 1 ? added the power dissipation characteristics table ................................................................................................................ 6 ? changed figure 7 ................................................................................................................................................................ 13 ? changed figure 8 ................................................................................................................................................................ 13 ? changed from: v cc1 to: v cci in figure 9 ............................................................................................................................ 14 ? changed figure 10 ............................................................................................................................................................... 14 ? changed table 1 .................................................................................................................................................................. 16 ? changed the test condition of cti of the table in table 1 ................................................................................................. 16 ? changed the min value of cti from " > 600 v to: 600 v .................................................................................................. 16 ? changed table 2 title from: din v vde 0884-10 (vde v 0884-10) and ul 1577 insulation characteristics to: insulation characteristics ...................................................................................................................................................... 17 ? changed table 2 .................................................................................................................................................................. 17 ? changed the table in regulatory information ....................................................................................................................... 18 ? deleted input-side and output-side from columns 1 and 2 of table 6 ..................................................................... 20 ? changed the application information section ...................................................................................................................... 22 ? changed the typical application section ............................................................................................................................ 22 ? added text and figure 17 to the detailed design procedure section ................................................................................. 23 changes from original (october 2014) to revision a page ? changed feature from: all agencies approvals pending to: all agencies approvals planned .......................................... 1 ? changed statement in the description from; " this device is certified to meet reinforced isolation requirements by vde and csa. " to: " this device is being reviewed for reinforced isolation certification by vde and csa. " ....................... 1 ? changed r io min value from: 10 9 to: 10 11 in the table 1 table ........................................................................................ 16 ? changed the first row of information in the regulatory information table ........................................................................... 18 copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 5 pin configuration and functions dw/dww package 16-pin soic top view pin functions pin i/o description name no. output enable 1. output pins on side 1 are enabled when en1 is high or open and in high- en1 7 i impedance state when en1 is low. output enable 2. output pins on side 2 are enabled when en2 is high or open and in high- en2 10 i impedance state when en2 is low. gnd1 2, 8 ? ground connection for v cc1 gnd2 9, 15 ? ground connection for v cc2 ina 3 i input, channel a inb 4 i input, channel b inc 12 i input, channel c ind 11 i input, channel d outa 14 o output, channel a outb 13 o output, channel b outc 5 o output, channel c outd 6 o output, channel d v cc1 1 ? power supply, v cc1 v cc2 16 ? power supply, v cc2 4 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f isolation 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v cc2 ind outd inb inc ina outb outa outc v cc1 gnd1 en2 gnd2 gnd2 gnd1 en1
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 6 specifications 6.1 absolute maximum ratings see (1) min max unit v cc1 , supply voltage (2) ? 0.5 6 v v cc2 inx voltage outx ? 0.5 v ccx + 0.5 (3) v enx i o output current ? 15 15 ma surge immunity 12.8 kv t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to the local ground terminal (gnd1 or gnd2) and are peak voltage values. (3) maximum voltage must not exceed 6 v 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 6000 v (esd) electrostatic discharge v charged device model (cdm), per jedec specification jesd22-c101, all 1500 pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions min nom max unit v cc1 , supply voltage 2.25 5.5 v v cc2 v cco (1) = 5 v ? 4 i oh high-level output current v cco (1) = 3.3 v ? 2 ma v cco (1) = 2.5 v ? 1 v cco (1) = 5 v 4 i ol low-level output current v cco (1) = 3.3 v 2 ma v cco (1) = 2.5 v 1 v ih high-level input voltage 0.7 v cci (1) v cci (1) v v il low-level input voltage 0 0.3 v cci (1) v dr signaling rate 0 100 mbps t j junction temperature (2) ? 55 150 c t a ambient temperature ? 55 25 125 c (1) v cci = input-side v cc ; v cco = output-side v cc . (2) to maintain the recommended operating conditions for t j , see thermal information . copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 6.4 thermal information dw (soic) dww (soic) thermal metric (1) unit 16 pins 16 pins r ja junction-to-ambient thermal resistance 78.9 78.9 r jc(top) junction-to-case(top) thermal resistance 41.6 41.1 r jb junction-to-board thermal resistance 43.6 49.5 c/w jt junction-to-top characterization parameter 15.5 15.2 jb junction-to-board characterization parameter 43.1 48.8 r jc(bottom) junction-to-case(bottom) thermal resistance n/a n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.5 power dissipation characteristics value unit p d maximum power dissipation by iso784 2 200 v cc1 = v cc2 = 5.5 v, t j = 150 c, p d1 maximum power dissipation by side-1 of iso784 2 c l = 15 pf, input a 50 mhz 50% duty cycle 100 mw square wave p d2 maximum power dissipation by side-2 of iso784 2 100 6 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 6.6 electrical characteristics, 5 v v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 4 ma; see figure 7 v cco (1) ? 0.4 v cco (1) ? 0.2 v v ol low-level output voltage i ol = 4 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 x v cco (1) v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx -10 cmti common-mode transient immunity v i = v cci (1) or 0 v; see figure 10 100 kv/ s supply current - ISO7842dw and ISO7842fdw en1 = en2 = 0v, v i = 0 v (ISO7842f) , i cc1 , i cc2 disable 1 1.5 ma v i = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) i cc1 , i cc2 disable 3.4 4.8 ma (ISO7842f) , v i = 0 v (ISO7842) v i = 0 v ISO7842f) , v i = v cci (1) i cc1 , i cc2 dc signal 2 2.7 ma (ISO7842) v i = v cci (1) (ISO7842f) , v i = 0 v i cc1 , i cc2 dc signal 4.4 6.1 ma (ISO7842) i cc1 , i cc2 1 mbps 3.3 4.6 ma all channels switching with square wave i cc1 , i cc2 10 mbps 4.2 5.6 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 13.7 16.6 ma supply current - ISO7842dww and ISO7842fdww en1 = en2 = 0v, v i = 0 v (ISO7842f) , i cc1 , i cc2 disable 1 1.5 ma v i = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) i cc1 , i cc2 disable 3.4 4.8 ma (ISO7842f) , v i = 0 v (ISO7842) v i = 0 v ISO7842f) , v i = v cci (1) i cc1 , i cc2 dc signal 2 2.8 ma (ISO7842) v i = v cci (1) (ISO7842f) , v i = 0 v i cc1 , i cc2 dc signal 4.4 6.3 ma (ISO7842) i cc1 , i cc2 1 mbps 3.4 4.7 ma all channels switching with square wave i cc1 , i cc2 10 mbps 4.3 5.9 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 14 17.3 ma (1) v cci = input-side v cc ; v cco = output-side v cc . copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 6.7 electrical characteristics, 3.3 v v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 2 ma; see figure 7 v cco (1) ? 0.4 v cco (1) ? 0.2 v v ol low-level output voltage i ol = 2 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 x v cco (1) v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx -10 cmti common-mode transient immunity v i = v cci (1) or 0 v; see figure 10 100 kv/ s supply current - ISO7842dw and ISO7842fdw en1 = en2 = 0 v, v i = 0 v (ISO7842f) , v i i cc1 , i cc2 disable 1 1.5 ma = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) (ISO7842f) , i cc1 , i cc2 disable 3.4 4.8 ma v i = 0 v (ISO7842) v i = 0 v (ISO7842f) , v i = v cci (1) i cc1 , i cc2 dc signal 2 2.7 ma (ISO7842) v i = v cci (1) (ISO7842f) , v i = 0 v i cc1 , i cc2 dc signal 4.4 6.1 ma (ISO7842) i cc1 , i cc2 1 mbps 3.3 4.5 ma all channels switching with square wave i cc1 , i cc2 10 mbps 4 5.2 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 10.8 12.9 ma supply current - ISO7842dww and ISO7842fdww en1 = en2 = 0 v, v i = 0 v (ISO7842f) , v i i cc1 , i cc2 disable 1 1.5 ma = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) (ISO7842f) , i cc1 , i cc2 disable 3.4 4.8 ma v i = 0 v (ISO7842) v i = 0 v (ISO7842f) , v i = v cci (1) i cc1 , i cc2 dc signal 2 2.8 ma (ISO7842) v i = v cci (1) (ISO7842f) , v i = 0 v i cc1 , i cc2 dc signal 4.4 6.3 ma (ISO7842) i cc1 , i cc2 1 mbps 3.4 4.7 ma all channels switching with square wave i cc1 , i cc2 10 mbps 4.1 5.5 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 11 13.6 ma (1) v cci = input-side v cc ; v cco = output-side v cc . 8 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 6.8 electrical characteristics, 2.5 v v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 1 ma; see figure 7 v cco (1) ? 0.4 v cco (1) ? 0.2 v v ol low-level output voltage i ol = 1 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 x v cco (1) v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx -10 cmti common-mode transient immunity v i = v cci (1) or 0 v; see figure 10 100 kv/ s supply current - ISO7842dw and ISO7842fdw en1 = en2 = 0 v, v i = 0 v (ISO7842f) , v i i cc1 , i cc2 disable 1 1.5 ma = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) (ISO7842f) , i cc1 , i cc2 disable 3.4 4.8 ma v i = 0 v (ISO7842) i cc1 , i cc2 dc signal v i = 0 v (ISO7842f) , v i = v cci (1) (ISO7842) 2 2.7 ma i cc1 , i cc2 dc signal v i = v cci (1) (ISO7842f) , v i = 0 v (ISO7842) 4.4 6.1 ma i cc1 , i cc2 1 mbps 3.2 4.5 ma all channels switching with square wave i cc1 , i cc2 10 mbps 3.7 5.1 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 8.9 10.8 ma supply current - ISO7842dww and ISO7842fdww en1 = en2 = 0 v, v i = 0 v (ISO7842f) , v i i cc1 , i cc2 disable 1 1.5 ma = v cci (1) (ISO7842) en1 = en2 = 0 v, v i = v cci (1) (ISO7842f) , i cc1 , i cc2 disable 3.4 4.8 ma v i = 0 v (ISO7842) i cc1 , i cc2 dc signal v i = 0 v (ISO7842f) , v i = v cci (1) (ISO7842) 2 2.8 ma i cc1 , i cc2 dc signal v i = v cci (1) (ISO7842f) , v i = 0 v (ISO7842) 4.4 6.3 ma i cc1 , i cc2 1 mbps 3.3 4.6 ma all channels switching with square wave i cc1 , i cc2 10 mbps 3.8 5.3 ma clock input; c l = 15 pf i cc1 , i cc2 100 mbps 9 11.5 ma (1) v cci = input-side v cc ; v cco = output-side v cc . copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 6.9 switching characteristics, 5 v v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time 6 11 16 see figure 7 pwd (1) pulse width distortion |t phl ? t plh | 0.55 4.1 t sk(o) (2) channel-to-channel output skew time same-direction channels 2.5 t sk(pp) (3) part-to-part skew time 4.5 ns t r output signal rise time 1.7 3.9 see figure 7 t f output signal fall time 1.9 3.9 t phz disable propagation delay, high-to-high impedance output 12 20 t plz disable propagation delay, low-to-high impedance output 12 20 enable propagation delay, high impedance-to-high output for 10 20 ns iso784 2 t pzh enable propagation delay, high impedance-to-high output for see figure 8 2 2.5 s iso784 2f enable propagation delay, high impedance-to-low output for 2 2.5 s iso784 2 t pzl enable propagation delay, high impedance-to-low output for 10 20 ns iso784 2f measured from the time v cc t fs default output delay time from input power loss 0.2 9 s goes below 1.7 v. see figure 9 t ie time interval error 0.90 ns 2 16 ? 1 prbs data at 100 mbps (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.10 switching characteristics, 3.3 v v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time 6 10.8 16 see figure 7 pwd (1) pulse width distortion |t phl ? t plh | 0.7 4.2 t sk(o) (2) channel-to-channel output skew time same-direction channels 2.2 t sk(pp) (3) part-to-part skew time 4.5 t r output signal rise time 0.8 3 ns see figure 7 t f output signal fall time 0.8 3 disable propagation delay, high-to-high impedance t phz 17 32 output disable propagation delay, low-to-high impedance t plz 17 32 output enable propagation delay, high impedance-to-high 17 32 ns output for iso784 2 t pzh see figure 8 enable propagation delay, high impedance-to-high 2 2.5 s output for iso784 2f enable propagation delay, high impedance-to-low 2 2.5 s output for iso784 2 t pzl enable propagation delay, high impedance-to-low 17 32 ns output for iso784 2f measured from the time v cc goes t fs default output delay time from input power loss 0.2 9 s below 1.7 v. see figure 9 t ie time interval error 0.91 ns 2 16 ? 1 prbs data at 100 mbps (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 10 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 6.11 switching characteristics, 2.5 v v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time 7.5 11.7 17.5 see figure 7 pwd (1) pulse width distortion |t phl ? t plh | 0.66 4.2 t sk(o) (2) channel-to-channel output skew time same-direction channels 2.2 t sk(pp) (3) part-to-part skew time 4.5 t r output signal rise time 1 3.5 ns see figure 7 t f output signal fall time 1.2 3.5 disable propagation delay, high-to-high impedance t phz 22 45 output disable propagation delay, low-to-high impedance t plz 22 45 output enable propagation delay, high impedance-to-high 18 45 ns output for iso784 2 t pzh see figure 8 enable propagation delay, high impedance-to-high 2 2.5 s output for iso784 2f enable propagation delay, high impedance-to-low 2 2.5 s output for iso784 2 t pzl enable propagation delay, high impedance-to-low 18 45 ns output for iso784 2f measured from the time v cc goes t fs default output delay time from input power loss 0.2 9 s below 1.7 v. see figure 9 t ie time interval error 0.91 ns 2 16 ? 1 prbs data at 100 mbps (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 6.12 typical characteristics t a = 25 c c l = 15 pf t a = 25 c c l = no load figure 1. supply current vs data rate (with 15-pf load) figure 2. supply current vs data rate (with no load) t a = 25 c t a = 25 c figure 3. high-level output voltage vs high-level output figure 4. low-level output voltage vs low-level output current current figure 5. power supply undervoltage threshold vs free-air figure 6. propagation delay time vs free-air temperature temperature 12 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f free-air temperature ( o c) power supply under-voltage threshold (v) -50 0 50 100 150 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 2.25 d005 v cc1 rising v cc1 falling v cc2 rising v cc2 falling free-air temperature ( o c) propagation delay time (ns) -60 -30 0 30 60 90 120 8 9 10 11 12 13 d006 t plh at 2.5 v t phl at 2.5 v t plh at 3.3 v t phl at 3.3 v t plh at 5.0 v t phl at 5.0 v high-level output current (ma) high-level output voltage (v) -15 -10 -5 0 0 1 2 3 4 5 6 d003 v cc at 2.5 v v cc at 3.3 v v cc at 5.0 v low-level output current (ma) low-level output voltage (v) 0 5 10 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d004d001 v cc at 2.5 v v cc at 3.3 v v cc at 5.0 v data rate (mbps) supply current (ma) 0 25 50 75 100 125 150 0 4 8 12 16 20 24 d001 i cc1 at 2.5 v i cc2 at 2.5 v i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5.0 v i cc2 at 5.0 v data rate (mbps) supply current (ma) 0 25 50 75 100 125 150 0 2 4 6 8 10 d002 i cc1 at 2.5 v i cc2 at 2.5 v i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5.0 v i cc2 at 5.0 v
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 7 parameter measurement information a. the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3ns, z o = 50 . at the input, 50 resistor is required to terminate input generator signal. it is not needed in actual application. b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 7. switching characteristics test circuit and voltage waveforms a. the input pulse is supplied by a generator having the following characteristics: prr 10 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 . b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 8. enable/disable propagation delay time test circuit and waveform copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: ISO7842 ISO7842f input generator 50 out en v o v i in 0 v c l see note a see note b 0 v v o v i 0.5 v 50% 50 out r = 1 k 1% l en v o v i in 3 v isolation barrier w 0 v 0 v v i 50% 0.5 v t pzh v o v oh t phz v / 2 cc v cc t pzl v cc v cco t plz v cco v ol isolation barrier r = 1 k 1% l input generator c l see note a see note b v / 2 cc v / 2 cc v / 2 cc isolation barrier v i 50 w in v o input generator note a c l out 50% 10% 90% v i v o t plh t phl 50% v cci 0 v 50% t r t f v oh 50% v ol note b
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com parameter measurement information (continued) a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 9. default output delay time test circuit and voltage waveforms a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 10. common-mode transient immunity test circuit 14 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f isolation barrier c = 0.1 f 1% in v oh or v ol out v cci + C v cm v cco c = 0.1 f 1% ! gndo gndi s1 + C pass-fail criteria C output must remainstable. c l ! note a v o out in in = 0 v (devices without suffix f) in = v (devices with suffix f) cc see note a c l v i 0 v t fs fs high v o v i 2.7 v 50% v cc v cc v ol v oh isolation barrier fs low
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 8 detailed description 8.1 overview iso784 2 employs an on-off keying (ook) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. the transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. the receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. if the en pin is low then the output goes to high impedance. iso784 2 also incorporates advanced circuit techniques to maximize the cmti performance and minimize the radiated emissions due the high frequency carrier and io buffer switching. the conceptual block diagram of a digital capacitive isolator, figure 11 , shows a functional block diagram of a typical channel. 8.2 functional block diagram figure 11. conceptual block diagram of a digital capacitive isolator also a conceptual detail of how the on/off keying scheme works is shown in figure 12 . figure 12. on-off keying (ook) based modulation scheme copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: ISO7842 ISO7842f tx in rx out carrier signal through isolation barrier tx in rx out oscillator emissions reduction techniques ook modulation tx signal conditioning rx signal conditioning envelope detection sio 2 based capacitive isolation barrier en transmitter receiver
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 8.3 feature description product channel direction rated isolation max data rate default output 2 forward, iso784 2 5700 v rms / 8000 v pk (1) 100 mbps high 2 reverse 2 forward, iso784 2f 5700 v rms / 8000 v pk (1) 100 mbps low 2 reverse (1) see regulatory information for detailed isolation ratings. 8.3.1 high voltage feature description table 1. package insulation and safety-related specifications over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit 16-dw 8 package shortest terminal-to-terminal distance l(i01) minimum air gap (clearance) mm through air 16-dww 14.5 package 16-dw 8 package minimum external tracking shortest terminal-to-terminal distance l(i02) (1) mm (creepage) across the package surface 16-dww 14.5 package tracking resistance (comparative cti din en 60112 (vde 0303-11); iec 60112; ul 746a 600 v tracking index) v io = 500 v, t a = 25 c 10 12 ? isolation resistance, input to r io output (2) v io = 500 v, 100 c t a max 10 11 ? barrier capacitance, input to c io v io = 0.4 x sin (2 ft), f = 1 mhz 2 pf output (2) c i input capacitance (3) v i = v cc /2 + 0.4 x sin (2 ft), f = 1 mhz, v cc = 5 v 2 pf (1) per jedec package dimensions. (2) all pins on each side of the barrier tied together creating a two-terminal device. (3) measured from input pin to ground. note creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 16 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 table 2. insulation characteristics parameter (1) test conditions specification unit dw dww dti distance through the insulation minimum internal gap (internal clearance) 21 21 m 1500 2000 v rms v iowm maximum isolation working voltage time dependent dielectric breakdown (tddb) test 2121 2828 v dc din v vde v 0884-10 (vde v 0884-10):2006-12 v test = v iotm maximum transient isolation v iotm t = 60 sec (qualification) 8000 8000 v pk voltage t= 1 sec (100% production) test method per iec 60065, 1.2/50 s waveform, v iosm maximum surge isolation voltage 8000 8000 v pk v test = 1.6 x v iosm = 12800 v pk (qualification) maximum repetitive peak isolation v iorm 2121 2828 v pk voltage method a, after input/output safety test subgroup 2/3, v pr = v iorm x 1.2, t = 10 s, 2545 3394 partial discharge < 5 pc method a, after environmental tests subgroup 1, v pr input-to-output test voltage v pr = v iorm x 1.6, t = 10 s, 3394 4525 v pk partial discharge < 5 pc method b1, v pr = v iorm x 1.875, t = 1 s (100% production test) 3977 5303 partial discharge < 5 pc r s isolation resistance v io = 500 v at t s > 10 9 > 10 9 ? pollution degree 2 2 ul 1577 v test = v iso = 5700 v rms , t = 60 sec (qualification), v iso withstanding isolation voltage v test = 1.2 x v iso = 6840 v rms , t = 1 sec (100% 5700 5700 v rms production) (1) climatic classification 55/125/21 table 3. iec 60664-1 ratings table parameter test conditions specification material group i rated mains voltage 600 v rms i ? iv overvoltage category / installation classification rated mains voltage 1000 v rms i ? iii copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 8.3.1.1 regulatory information dw package certifications are complete. dww package certifications are planned. table 4. regulatory information vde csa ul cqc certified according to din v vde approved under csa certified according to ul 1577 v 0884-10 (vde v 0884- component acceptance notice certified according to gb 4943.1- component recognition 10):2006-12 and din en 60950- 5a, iec 60950-1, iec 61010-1, 2011 program 1 (vde 0805 teil 1):2011-01 and iec 60601-1 reinforced insulation per csa 61010-1-12 and iec 61010-1 3rd ed., 300 v rms max working voltage; reinforced insulation maximum transient isolation reinforced insulation per csa voltage, 8000 v pk ; 60950-1-07+a1+a2 and iec reinforced insulation, altitude maximum repetitive peak 60950-1 2nd ed., 800 v rms single protection, 5700 v rms (1) 5000 m, tropical climate, 250 v rms isolation voltage, 2121 v pk max working voltage (pollution maximum working voltage (dw), 2828 v pk (dww); degree 2, material group i) ; maximum surge isolation 2 mopp (means of patient voltage, 8000 v pk protection) per csa 60601- 1:14 and iec 60601-1 ed. 3.1, 250 v rms (354 v pk ) max working voltage master contract number: certificate number: certificate number: 40040142 file number: e181974 220991 cqc15001121716 (1) production tested 6840 v rms for 1 second in accordance with ul 1577. 18 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 8.3.1.2 safety limiting values safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. table 5. safety limiting values parameter test conditions min typ max unit r ja = 78.9 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c 288 safety input, output, or supply i s r ja = 78.9 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c 440 ma current r ja = 78.9 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c 576 p s safety input, output, or total mw r ja = 78.9 c/w, t j = 150 c, t a = 25 c 1584 power t s maximum safety temperature 150 c the maximum safety temperature is the maximum junction temperature specified for the device. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information is that of a device installed on a high-k test board for leaded surface mount packages. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance figure 13. thermal derating curve for safety limiting figure 14. thermal derating curve for safety limiting current per vde power per vde copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: ISO7842 ISO7842f ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 100 200 300 400 500 600 700 d014 v cc1 = v cc2 = 2.75 v v cc1 = v cc2 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 1600 1800 d015 power
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 8.4 device functional modes iso784 2 functional modes are shown in table 6 . table 6. function table (1) output input output v cci v cco enable comments (inx) (2) (outx) ( enx) h h or open h normal operation: a channel output assumes the logic state of its input. l h or open l pu pu default mode: when inx is open, the corresponding channel output open h or open default goes to its default logic state. default= high for iso784 2 and low for iso784 2f. a low value of output enable causes the outputs to be high- x pu x l z impedance default mode: when v cci is unpowered, a channel output assumes the logic state based on the selected default option. default= high for iso784 2 and low for iso784 2f. pd pu x h or open default when v cci transitions from unpowered to powered-up, a channel output assumes the logic state of its input. when v cci transitions from powered-up to unpowered, channel output assumes the selected default state. when v cco is unpowered, a channel output is undetermined (3) . x pd x x undetermined when v cco transitions from unpowered to powered-up, a channel output assumes the logic state of its input (1) v cci = input-side v cc ; v cco = output-side v cc ; pu = powered up (v cc 2.25 v); pd = powered down (v cc 1.7 v); x = irrelevant; h = high level; l = low level ; z = high impedance (2) a strongly driven input signal can weakly power the floating v cc via an internal protection diode and cause undetermined output. (3) the outputs are in undetermined state when 1.7 v < v cci , v cco < 2.25 v. 20 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 8.4.1 device i/o schematics figure 15. device i/o schematics copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: ISO7842 ISO7842f inx 1.5 m w 985 w input output v cci v cci enx 1970 w enable v cco v cco v cco v cci 2 m w outx v cco ~20 w v cci v cco
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the iso784 2 is a high-performance, quad-channel digital isolator with 5.7 kv rms isolation voltage per ul 1577. the device comes with enable pins on each side which can be used to put the respective outputs in high impedance for multi master driving applications and reduce power consumption. iso784 2 uses single-ended cmos-logic switching technology. its supply voltage range is from 2.25 v to 5.5 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (that is, c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application typical isolated rs-232 interface implementation is shown in figure 16 . figure 16. isolated rs-232 interface 22 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f v cc1 v cc2 gnd1 gnd2 outa 16 14 12 2,8 9,15 p3.1 p3.0 uca0txd uca0rxd 11 15 16 12 4 xout xin 56 2 msp430 f2132 ina outd 1 35 4 6 ISO7842 dvss dvcc 0.1 f 0.1 f 0.1 f en1 en2 7 10 inb 13 11 outb inc ind 16 0.1 f outc vcc gnd 15 t1in 9 11 12 10 c2- 3 r1out t2in 14 13 57 8 v s- 64 21 r2out v s+ c1+ c1- c2+ trs232 4.7k 4.7k r1in t1out r2in t2out 1 f 1 f 1 f 1 f txd rxd rst cst isognd 10 f 0.1 f mbr0520l mbr0520l 1:2.1 0.1 f 31 d2 sn6501 d1 vcc 4,5 2 gnd 3.3v in on gnd out 1 54 3 lp2985-50 3.3 f 10 f iso-barrier v in 5v iso 2 bp 10nf
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 typical application (continued) 9.2.1 design requirements for iso784 2, use the parameters shown in table 7 . table 7. design parameters parameter value supply voltage 2.25 to 5.5 v decoupling capacitor between v cc1 and gnd1 0.1 f decoupling capacitor from v cc2 and gnd2 0.1 f 9.2.2 detailed design procedure unlike optocouplers, which need external components to improve performance, provide bias, or limit current, iso784 2 only needs two external bypass capacitors to operate. figure 17. typical ISO7842 circuit hook-up 9.2.2.1 electromagnetic compatibility (emc) considerations many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (esd), electrical fast transient (eft), surge and electromagnetic emissions. these electromagnetic disturbances are regulated by international standards such as iec 61000-4-x and cispr 22. although system-level performance and reliability depends, to a large extent, on the application board design and layout, the iso784 2 incorporate many chip-level design improvements for overall system robustness. some of these improvements include: ? robust esd protection for input and output signal pins and inter-chip bond pads. ? low-resistance connectivity of esd cells to supply and ground pins. ? enhanced performance of high voltage isolation capacitor for better tolerance of esd, eft and surge events. ? bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. ? pmos and nmos devices isolated from each other by using guard rings to avoid triggering of parasitic scrs. ? reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: ISO7842 ISO7842f isolation 12 3 4 1615 14 13 56 7 8 1211 10 9 ISO7842 ina gnd1 v cc1 gnd1 gnd2 gnd2 inb inc outa outc outb en ind outd v cc2 0.1 p f 0.1 p f ind gnd2 gnd2 outc v cc2 en2 outb outa gnd1 v cc1 outd inb en1 ina inc gnd1
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 9.2.3 application curve typical eye diagram of iso784 2 indicate low jitter and wide open eye at the maximum data rate of 100 mbps. figure 18. eye diagram at 100 mbps prbs, 5 v and 25 c 10 power supply recommendations to ensure reliable operation at all data rates and supply voltages, a 0.1- f bypass capacitor is recommended at input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments' sn6501 . for such applications, detailed power supply design and transformer selection recommendations are available in sn6501 data sheet ( sllsea0 ). 24 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 19 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pf/inch 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see application note slla284 , digital isolator design guide . 11.1.1 pcb material for digital circuit boards operating below 150 mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 epoxy-glass as pcb material. fr-4 (flame retardant 4) meets the requirements of underwriters laboratories ul94-v0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics. 11.2 layout example figure 19. layout example schematic copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: ISO7842 ISO7842f 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces , pads, and vias ground plane power plane low-speed traces high-speed traces
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation see the isolation glossary (slla353) 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8. related links technical tools & support & parts product folder sample & buy documents software community ISO7842 click here click here click here click here click here ISO7842f click here click here click here click here click here 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 26 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: ISO7842 ISO7842f www.ti.com package outline c typ 10.639.97 2.65 max 14x 1.27 16x 0.510.31 2x 8.89 typ 0.380.25 0 - 8 0.30.1 (1.4) 0.25 gage plane 1.270.40 a note 3 10.510.1 b note 4 7.67.4 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm, per side. 5. reference jedec registration mo-013, variation aa. 1 16 0.25 c a b 9 8 pin 1 idarea seating plane 0.1 c see detail a typical detail a scale 1.500
ISO7842 , ISO7842f sllsej0d ? october 2014 ? revised december 2015 www.ti.com 28 submit documentation feedback copyright ? 2014 ? 2015, texas instruments incorporated product folder links: ISO7842 ISO7842f www.ti.com example board layout (9.75) 0.07 max all around 0.07 min all around (9.3) 14x (1.27) 16x (1.65) 16x (0.6) 14x (1.27) 16x (2) 16x (0.6) 4221009/a 08/2013 symm soic - 2.65 mm max height dw0016b soic symm see details 1 8 9 16 symm hv / isolation option 8.1 mm clearance/creepage notes: (continued) 6. publication ipc-7351 may have alternate designs.7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder maskopening non solder mask defined opening solder mask details solder mask metal solder mask defined scale:4x land pattern example symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage see details
ISO7842 , ISO7842f www.ti.com sllsej0d ? october 2014 ? revised december 2015 copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: ISO7842 ISO7842f www.ti.com example stencil design 16x (1.65) 16x (0.6) 14x (1.27) (9.75) 16x (2) 16x (0.6) 14x (1.27) (9.3) 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 8 9 16 hv / isolation option 8.1 mm clearance/creepage based on 0.125 mm thick stencil solder paste example scale:4x symm symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage
www.ti.com package outline c 0 -8 17.4 17.1 14x 1.27 16x 0.51 0.31 (2.286) 2.65 max 2x 8.89 0.3 0.1 typ 0.28 0.22 (1.625) a note 3 10.4 10.2 b note 4 14.1 13.9 0.25 gage plane 1.1 0.6 soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0,15 mm per side. 4. this dimension does not include interlead flash. pin 1 id area 1 8 0.25 a b c 9 16 0.1 c seating plane see detail a detail a typical scale 1.000
www.ti.com example board layout 14x (1.27) (16.25) 0.07 max all around 0.07 min all around 16x (0.6) 16x (2) (14.25) (14.5) 16x (1.875) 16x (0.6) (16.375) 14x (1.27) soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 symm symm land pattern example standard scale:3x 1 8 9 16 notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal opening solder mask non solder mask defined (preferred) solder mask details solder mask metal under solder mask opening solder mask defined land pattern example pcb clearance & creepage optimized scale:3x symm symm 1 8 9 16
www.ti.com example stencil design (16.25) 14x (1.27) 16x (2) 16x (0.6) 16x (1.875) 16x (0.6) 14x (1.27) (16.375) soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. solder paste example standard based on 0.125 mm thick stencil scale:4x symm symm 1 8 9 16 solder paste example pcb clearance & creepage optimized based on 0.125 mm thick stencil scale:4x symm symm 1 8 9 16
package option addendum www.ti.com 19-dec-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ISO7842dw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842 ISO7842dwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842 ISO7842dww preview soic dww 16 45 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842 ISO7842fdw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842f ISO7842fdwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842f ISO7842fdww preview soic dww 16 45 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7842f (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 19-dec-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ISO7842dwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 ISO7842fdwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 package materials information www.ti.com 8-dec-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ISO7842dwr soic dw 16 2000 367.0 367.0 38.0 ISO7842fdwr soic dw 16 2000 367.0 367.0 38.0 package materials information www.ti.com 8-dec-2015 pack materials-page 2
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2015, texas instruments incorporated

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